IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 16

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–8
Table 1–5. 2D Median Filter Performance (Part 2 of 2)
Table 1–6. Alpha Blending Mixer Performance
Video and Image Processing Suite User Guide
Median filtering 352×288 pixel two color frames using a 5×5 kernel of pixels.
7×7 median filtering 352×288 pixel monochrome video.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Alpha blending an on-screen display within a region of 1,024×768 pixel 10-bit Y’CbCr 4:4:4 video. Alpha blending is
performed using 16 levels of opacity from fully opaque to fully translucent.
Drawing a picture-in-picture window over the top of a 128×128 pixel background image in 8-bit R’G’B’ color.
Rendering two images over 352×240 pixel background 8-bit R’G’B’ video.
Using alpha blending to composite three layers over the top of PAL resolution background video in 8-bit monochrome.
Alpha blending is performed using 256 levels of opacity from fully opaque to fully translucent.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Device Family
Device Family
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Table
Table
Alpha Blending Mixer
(2)
(2)
(2)
(2)
(2)
(2)
(2)
1–5:
1–6:
(1)
(1)
(1)
(1)
(1)
(1)
Combinational
Combinational
Table 1–6
LUTs/ALUTs
LUTs/ALUTs
10,801
5,402
2,698
4,863
1,068
1,814
1,368
1,162
984
748
842
597
824
shows the performance figures for the Alpha Blending Mixer.
Registers
Registers
11,192
Logic
1,154
5,667
3,832
7,296
Logic
1,236
2,143
1,283
1,291
732
941
529
709
28,160
28,160
16,896
16,896
3,072
Bits
Bits
752
752
752
752
752
752
752
752
Memory
Memory
M9K
M9K
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Chapter 1: About This MegaCore Function Suite
(9×9)
(9×9)
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4
6
DSP Blocks
DSP Blocks
Performance and Resource Utilization
January 2011 Altera Corporation
(18×18)
(18×18)
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2
6
235.07
274.35
216.59
262.61
200.72
324.36
180.51
217.91
309.98
219.88
317.86
(MHz)
(MHz)
364.7
294.2
f
f
MAX
MAX