IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 136

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–56
Video and Image Processing Suite User Guide
1
Figure 5–26 on page 5–56
polyphase mode.
Figure 5–26. Polyphase Mode Scaler Block Diagram
Data from multiple lines of the input image are assembled into line buffers–one for
each vertical tap. These data are then fed into parallel multipliers, before summation
and possible loss of precision. The results are gathered into registers–one for each
horizontal tap. These are again multiplied and summed before precision loss down to
the output data bit width.
The progress of data through the taps (line buffer and register delays) and the
coefficient values in the multiplication are controlled by logic that is not present in the
diagram. Refer to
Resource Usage
Consider an instance of the polyphase scaler with N
taps. B
B
for the vertical coefficients. It is equal to the sum of integer bits and fraction bits for
the vertical coefficients, plus one if coefficients are signed.
v
is the bit width of the vertical coefficients and is derived from the user parameters
data
Cv
is the bit width of the data samples.
Ch
0
0
“Algorithmic Description” on page
shows the flow of data through an instance of the scaler in
Cv
Ch
1
1
Register Delay
Line Buffer
Bit Narrowing
Delay
Bit Narrowing
v
Cv
Ch
vertical taps and N
5–58.
Nv
Nh
Line Buffer
Register Delay
Chapter 5: Functional Descriptions
Delay
January 2011 Altera Corporation
h
horizontal
Scaler