IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 191

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Control Register Maps
Frame Reader
Frame Reader
Table 7–12. Frame Reader Register Map for Run-Time Control
Gamma Corrector
January 2011 Altera Corporation
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Address
Control
Status
Interrupt
Frame Select
Frame 0 Base
Address
Frame 0 Words
Frame 0 Single
Cycle Color
Patterns
Frame 0
Reserved
Frame 0 Width
Frame 0 Height
Frame 0
Interlaced
Frame 1 Base
Address
Frame 1 Words
Frame 1 Single
Cycle Color
Patterns
Frame 1
Reserved
Frame 1 Width
Frame 1 Height
Frame 1
Interlaced
Register
The width of each register of the frame reader is 32 bits. The control data is read once
at the start of each frame. The registers may be safely updated during the processing
of a frame.
The Gamma Corrector can have up to three Avalon-MM slave interfaces. There is a
separate slave interface for each channel in parallel.
Table 7–15 on page 7–12
Bit 0 of this register is the Go bit. Setting this bit to 1 causes the Frame Reader to start
outputting data. Bit 1 of the Control register is the interrupt enable. Setting bit 1 to 1,
enables the end of frame interrupt.
Bit 0 of this register is the Status bit. All other bits are unused. Refer to
Slave Interfaces” on page 4–17
Bit 1 of this register is the end of frame interrupt bit. All other bits are unused. Writing a 1
to bit 1 resets the end of frame interrupt.
This register selects between frame 0 and frame 1 for next output. Frame 0 is selected by
writing a 0 here, frame is selected by writing a 1 here.
The 32-bit base address of the frame.
The number of words (reads from the master port) to read from memory for the frame.
The number of single-cycle color patterns to read for the frame.
Reserved for future use.
The Width to be used for the control packet associated with frame 0.
The Height to be used for the control packet associated with frame 0.
The interlace nibble to be used for the control packet associated with frame 0.
The 32-bit base address of the frame.
The number of words (reads from the master port) to read from memory for the frame.
The number of single-cycle color patterns to read for the frame.
Reserved for future use.
The Width to be used for the control packet associated with the frame.
The Height to be used for the control packet associated with the frame.
The interlace nibble to be used for the control packet associated with the frame.
Table 7–12
describes the Frame Reader runtime control registers.
describe the control register maps for these interfaces.
for full details.
Description
Table
Video and Image Processing Suite User Guide
7–13,
Table 7–14
“Avalon-MM
and
7–11