IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 44

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–8
Table 3–8. Clocked Video Output Parameter Settings (Part 2 of 2)
Video and Image Processing Suite User Guide
Frame / Field 1:
Vertical front porch
Frame / Field 1:
Vertical back porch
Interlaced and Field 0:
F rising edge line
Interlaced and Field 0:
F falling edge line
Interlaced and Field 0:
Vertical blanking rising
edge line
Interlaced and Field 0:
Ancillary packet
insertion line
Interlaced and Field 0:
Vertical blanking
Interlaced and Field 0:
Vertical sync
Interlaced and Field 0:
Vertical front porch
Interlaced and Field 0:
Vertical back porch
Pixel FIFO size
FIFO level at which to
start output
Video in and out use the
same clock
Use control port
Runtime configurable
video modes
Accept synchronization
outputs
Width of “vid_std”
Notes to
(1) This parameter is available only when Use control port is on.
Parameter
Table
(1)
3–8:
0–65,536,
Default = 4
0–65,536,
Default = 36
0–65,536,
Default = 0
0–65,536,
Default = 18
0–65,536,
Default = 0
0–65,536,
Default = 0
0–65,536,
Default = 0
0–65,536,
Default = 0
0–65,536,
Default = 0
0–65,536,
Default = 0
32–(memory limit),
Default = 1,920
0–(memory limit),
Default = 0
On or Off
On or Off
1–14, Default = 1
No, Yes
0–16
Value
Choose the number of lines in the vertical front porch period for
Frame/Field 1.
Choose the number of lines in the vertical back porch period for
Frame/Field 1.
Choose the line when the rising edge of the field bit occurs for Interlaced
and Field 0.
Choose the line when the rising edge of the vertical blanking bit for Field 0
occurs for Interlaced and Field 0.
Choose the line when the vertical blanking rising edge occurs for
Interlaced and Field 0.
Choose the line where ancillary packet insertion starts.
Choose the number of lines in the vertical front porch period for Interlaced
and Field 0.
Choose the number of lines in the vertical back porch period for Interlaced
and Field 0.
Choose the number of lines in the vertical front porch period for Interlaced
and Field 0.
Choose the number of lines in the vertical back porch period for Interlaced
and Field 0.
Choose the required FIFO depth in pixels (limited by the available on-chip
memory).
Choose the fill level that the FIFO must have reached before the output
video starts.
Turn on if you want to use the same signal for the input and output video
image stream clocks.
Turn on to use the optional Avalon-MM control port.
Choose the number of runtime configurable video output modes that are
required when you are using the Avalon-MM control port.
Specifies whether the synchronization outputs are used:
■
■
Specifies the width of the vid_std bus.
No - Not used
Yes - Synchronization outputs, from the Clocked Video Input MegaCore
function, (sof, sof_locked) are used
Description
January 2011 Altera Corporation
Chapter 3: Parameter Settings
Clocked Video Output