IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 73

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Interfaces
Avalon-ST Video Protocol
Figure 4–13. Timing Diagram Showing R’G’B’ Transferred in Sequence
Note to
(1) The startofpacket and endofpacket signals are not shown but are always low during the sequence shown in this figure.
January 2011 Altera Corporation
Figure
dout_data 7:0
4–13:
din_data 7:0
dout_ready
dout_valid
din_ready
din_valid
clock
Example 2 (Data Transferred in Sequence)
This example shows how a number of pixels from the middle of a frame could be
processed by another MegaCore function. This time handling a color pattern that has
planes B'G'R' in sequence. This example does not show the start of packet and end of
packet signals because these are always low during the middle of a packet.
The bits per pixel per color plane and color pattern are shown in
Table 4–9. Parameters for Example of Data Transferred in Sequence
Figure 4–13
This example is similar to
accept data in sequence rather than parallel. The signals shown in the timing diagram
are therefore the same but with the exception that the two data ports are only 8 bits
wide.
The sequence of events shown in
1. Initially, din_ready is logic '1'. The source driving the input port sets din_valid to
2. The source holds din_valid at logic '1' and the green color value G
3. The corresponding red color value R
logic '1' and puts the blue color value B
1.
B
m,n
Bits per Color Sample
shows how a number of pixels from the middle of a frame are processed.
2.
G
G
Color Pattern
0,0
m,n
Parameter
3.
R
m,n
Figure 4–12 on page 4–13
4.
B
B
m+1,n
m,n
Figure 4–13
5.
G
G
m+1,n
1,0
m,n
m,n
is input.
6.
on the din_data port.
is:
7.
except that it is configured to
Video and Image Processing Suite User Guide
8.
B
G
G
Value
0,0
m,n
G
8
Table
R
9.
R
R
m+1,n
m,n
m,n
4–9.
is input.
4–15