EVAL-ADAU1761Z Analog Devices Inc, EVAL-ADAU1761Z Datasheet - Page 11

• Manufacturer Part Number: EVAL-ADAU1761Z
• Description: Eval Board For ADAU1761
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r

Specifications of EVAL-ADAU1761Z

• Main Purpose: Audio, CODEC
• Embedded: Yes, DSP
• Utilized Ic / Part: ADAU1761
• Primary Attributes: Stereo, 24-Bit, 8 ~ 96 kHz Sampling Rate, GUI Tool
• Secondary Attributes: I²C and GPIO Interfaces, 2 Differential and 1 Stereo Single-Ended Analog Inputs and Outputs
• Silicon Manufacturer: Analog Devices
• Core Architecture: SigmaDSP
• Silicon Core Number: ADAU1761
• Silicon Family Name: SigmaDSP
• Application Sub Type: Audio
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIGITAL TIMING SPECIFICATIONS
−40°C < T
Table 7. Digital Timing
Parameter
MASTER CLOCK
SERIAL PORT
SPI PORT
I
DIGITAL MICROPHONE
2
C PORT
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CCLK
SCL
MP
MP
MP
MP
BIL
BIH
LIS
LIH
SIS
SIH
SODM
CCPL
CCPH
CLS
CLH
CLPH
CDS
CDH
COD
SCLH
SCLL
SCS
SCH
DS
SCR
SCF
SDR
SDF
BFT
DCF
DCR
DDV
DDH
A
< +85°C, IOVDD = 3.3 V ± 10%.
t
74
37
24.7
18.5
5
5
5
5
5
5
10
10
5
10
10
5
5
0.6
1.3
0.6
0.6
100
0.6
22
0
MIN
Limit
t
488
244
162.7
122
50
10
50
400
300
300
300
300
10
10
30
12
MAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
Rev. C | Page 11 of 92
Description
MCLK period, 256 × f
MCLK period, 512 × f
MCLK period, 768 × f
MCLK period, 1024 × f
BCLK pulse width low.
BCLK pulse width high.
LRCLK setup. Time to BCLK rising.
LRCLK hold. Time from BCLK rising.
DAC_SDATA setup. Time to BCLK rising.
DAC_SDATA hold. Time from BCLK rising.
ADC_SDATA delay. Time from BCLK falling in master mode.
CCLK frequency.
CCLK pulse width low.
CCLK pulse width high.
CLATCH setup. Time to CCLK rising.
CLATCH hold. Time from CCLK rising.
CLATCH pulse width high.
CDATA setup. Time to CCLK rising.
CDATA hold. Time from CCLK rising.
COUT three-stated. Time from CLATCH rising.
SCL frequency.
SCL high.
SCL low.
Setup time; relevant for repeated start condition.
Hold time. After this period, the first clock is generated.
Data setup time.
SCL rise time.
SCL fall time.
SDA rise time.
SDA fall time.
Bus-free time. Time between stop and start.
R
Digital microphone clock fall time.
Digital microphone clock rise time.
Digital microphone delay time for valid data.
Digital microphone delay time for data three-stated.
LOAD
= 1 MΩ, C
LOAD
= 14 pF.
S
S
S
mode.
mode.
mode.
S
mode.
ADAU1761