EVAL-ADAU1761Z Analog Devices Inc, EVAL-ADAU1761Z Datasheet - Page 60

• Manufacturer Part Number: EVAL-ADAU1761Z
• Description: Eval Board For ADAU1761
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r

Specifications of EVAL-ADAU1761Z

• Main Purpose: Audio, CODEC
• Embedded: Yes, DSP
• Utilized Ic / Part: ADAU1761
• Primary Attributes: Stereo, 24-Bit, 8 ~ 96 kHz Sampling Rate, GUI Tool
• Secondary Attributes: I²C and GPIO Interfaces, 2 Differential and 1 Stereo Single-Ended Analog Inputs and Outputs
• Silicon Manufacturer: Analog Devices
• Core Architecture: SigmaDSP
• Silicon Core Number: ADAU1761
• Silicon Family Name: SigmaDSP
• Application Sub Type: Audio
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1761
R11: ALC Control 0, 16,401 (0x4011)
Bit 7
Table 45. ALC Control 0 Register
Bits
[7:6]
[5:3]
[2:0]
PGASLEW[1:0]
Bit Name
PGASLEW[1:0]
ALCMAX[2:0]
ALCSEL[2:0]
Bit 6
Description
PGA volume slew time when the ALC is off. The slew time is the period of time that a volume increase or decrease
takes to ramp up or ramp down to the target volume set in Register R8 (left differential input volume control)
and Register R9 (right differential input volume control).
Setting
00
01
10
11
The maximum ALC gain sets a limit to the amount of gain that the ALC can provide to the input signal. This
protects small signals from excessive amplification.
Setting
000
001
010
011
100
101
110
111
ALC select. These bits set the channels that are controlled by the ALC. When set to right only, the ALC responds
only to the right channel input and controls the gain of the right PGA amplifier only. When set to left only, the
ALC responds only to the left channel input and controls the gain of the left PGA amplifier only. When set to
stereo, the ALC responds to the greater of the left or right channel and controls the gain of both the left and
right PGA amplifiers. DSP control allows the PGA gain to be set within the DSP or from external GPIO inputs.
These bits must be off if manual control of the volume is desired.
Setting
000
001
010
011
100
101
110
111
Bit 5
Bit 4
ALCMAX[2:0]
Slew Time
24 ms (default)
48 ms
96 ms
Off
Maximum ALC Gain
−12 dB (default)
−6 dB
0 dB
6 dB
12 dB
18 dB
24 dB
30 dB
Channels
Off (default)
Right only
Left only
Stereo
DSP control
Reserved
Reserved
Reserved
Rev. C | Page 60 of 92
Bit 3
Bit 2
Bit 1
ALCSEL[2:0]
Bit 0