LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 129

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

MDPE
BF
ABRT
SSI
SIR
R
IID
Operating Registers
Master Data Parity Error
This bit is set when the LSI53C825A as a master detects
a data parity error, or a target device signals a parity error
during a data phase. This bit is completely disabled by
the Master Parity Error Enable bit (bit 3 of
(CTEST4)).
Bus Fault
This bit is set when a PCI bus fault condition is detected.
A PCI bus fault can only occur when the LSI53C825A is
bus master, and is defined as a cycle that ends with a
Bad Address or Target Abort Condition.
Aborted
This bit is set when an abort condition occurs. An abort
condition occurs when a software abort command is
issued by setting bit 7 of the
register.
Single Step Interrupt
If the Single Step Mode bit in the
register is set, this bit is set and an interrupt generated
after successful execution of each SCRIPTS instruction.
SCRIPTS Interrupt Instruction Received
This status bit is set whenever an interrupt instruction is
evaluated as true.
Reserved
Illegal Instruction Detected
This status bit is set any time an illegal or reserved
instruction opcode is detected, whether the LSI53C825A
is operating in single step mode or automatically
executing SCSI SCRIPTS.
Any of the following conditions during instruction
execution also sets this bit:
The LSI53C825A is executing a Wait Disconnect
instruction and the SCSI REQ line is asserted without
a disconnect occurring.
A Block Move instruction is executed with 0x000000
loaded into the
indicating there are zero bytes to move.
DMA Byte Counter (DBC)
Interrupt Status (ISTAT)
DMA Control (DCNTL)
Chip Test Four
register,
4-41
6
5
4
3
2
1
0