LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 163

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

When performing consecutive 8-bit reads of the
SCSI Interrupt Status Zero
(SIST1)
periods between the reads to ensure the interrupts clear properly. Also,
if reading the registers when both the
DIP bits may not be set, read the
SCSI Interrupt Status One (SIST1)
(DSTAT)
on interrupts refer to
M/A
CMP
SEL
RSL
SGE
Operating Registers
registers (in any order), insert a delay equivalent to 12 clock
register to avoid missing a SCSI interrupt. For more information
Initiator Mode: Phase Mismatch; Target Mode:
SATN/ Active
In the initiator mode, this bit is set if the SCSI phase
asserted by the target does not match the instruction.
The phase is sampled when SREQ/ is asserted by the
target. In the target mode, this bit is set when the SATN/
signal is asserted by the initiator.
Function Complete
This bit is set when an arbitration only or full arbitration
sequence is completed.
Selected
This bit is set when the LSI53C825A is selected by
another SCSI device. The Enable Response to Selection
bit must be set in the
the
(RESPID1)
LSI53C825A to respond to selection attempts.
Reselected
This bit is set when the LSI53C825A is reselected by
another SCSI device. The Enable Response to
Reselection bit must be set in the
register (and the
Response ID One (RESPID1)
chip’s ID) for the LSI53C825A to respond to reselection
attempts.
SCSI Gross Error
This bit is set when the LSI53C825A encounters a SCSI
Gross Error Condition. The following conditions can result
in a SCSI Gross Error Condition:
Data Underflow – reading the SCSI FIFO when no
data is present.
Response ID Zero (RESPID0)
Chapter 2, “Functional Description.”
registers must hold the chip’s ID) for the
(SIST0), and
SCSI Interrupt Status Zero (SIST0)
Response ID Zero (RESPID0)
registers before the
SCSI Chip ID (SCID)
Interrupt Status (ISTAT)
SCSI Interrupt Status One
registers must hold the
DMA Status
and
SCSI Chip ID (SCID)
Response ID One
DMA Status
register (and
(DSTAT),
SIP and
and
and
4-75
7
6
5
4
3