LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 84

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

3.1.8 External Memory Interface Signals
Table 3.9
3-14
Name
MAS0/
MAS1/
MAD[7:0]
MWE/
MOE/
MCE/
GPIO2_
MAS2/
Pin No.
137/179/A8
136/178/B8
139/181/C7
140/182/B7
141/183/A7
59, 60, 61,
62, 64, 65,
68/87/J8
External Memory Interface Signals
66, 67
Table 3.9
group:
Signal Descriptions
Type Description
I/O
I/O
O
O
O
O
O
describes the signals for the External Memory Interface Signals
Memory Address Strobe 0. This pin is used to latch in the least
significant address byte of an external EPROM or flash memory.
Since the LSI53C825A moves addresses eight bits at a time, this pin
connects to the clock of an external bank of flip-flops which are used
to assemble up to a 20-bit address for the external memory.
Memory Address Strobe 1. This pin is used to latch in the address
byte corresponding to address bits [15:8] of an external EPROM or
flash memory. Since the LSI53C825A moves addresses eight bits at
a time, this pin connects to the clock of an external bank of flip-flops
which assemble up to a 20-bit address for the external memory.
Memory Address/Data Bus. This bus is used in conjunction with the
memory address strobe pins and external address latches to
assemble up to a 20-bit address for an external EPROM or flash
memory. This bus will put out the most significant byte first and finish
with the least significant bits. It is also used to write data to a flash
memory or read data into the chip from external EPROM/flash
memory. See
Memory Write Enable. This pin is used as a write enable signal to
an external flash memory.
Memory Output Enable. This pin is used as an output enable signal
to an external EPROM or flash memory during read operations.
Memory Chip Enable. This pin is used as a chip enable signal to
an external EPROM or flash memory device.
General Purpose I/O pin. Optionally, this pin is used as a Memory
Address Strobe 2 if an external memory with more than 16 bits of
addressing is specified by the pull-down resistors at power-up and
bit 0 in the
Expansion ROM Base Address
Section 3.2, “MAD Bus Programming,”
register is set.
for more details.