LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 47

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Table 2.5
2.4.8 DMA FIFO
Figure 2.1
Transfers
DPH
0
0
1
1
Key:
DHP = Disable Halt on SATN/ or Parity Error (bit 5,
PAR = Parity Error (bit 0,
Deep
134
.
. .
SCSI Parity Errors and Interrupts
DMA FIFO Sections
Byte Lane 3
PAR
0
1
0
1
8 Bits
The DMA FIFO is 4 bytes wide by 134 transfers deep. The DMA FIFO is
illustrated in
LSI53C8XX family, the user may set the DMA FIFO size to 88 bytes by
clearing the DMA FIFO Size bit, bit 5 in the
register.
PCI Cache Mode
SCSI Interrupt Enable Zero
Description
Halts when a parity error occurs in target or initiator mode and will
not generate an interrupt.
Halts when a parity error occurs in target mode and will generate
an interrupt in target or initiator mode.
Does not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt will not be generated.
Does not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt will be generated.
Figure
Byte Lane 2
8 Bits
2.1. To assure compatibility with older products in the
32 Bytes Wide
SCSI Control One
(SIEN0).
Byte Lane 1
8 Bits
Chip Test Five (CTEST5)
(SCNTL1).
Byte Lane 0
8 Bits
2-23
.
. .