LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 45

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.4.7 Parity Options
Table 2.3
BIt Name
Assert SATN/ on Parity
Errors
Enable Parity Checking
Assert Even SCSI Parity
Disable Halt on SATN/ or
a Parity Error (Target
Mode Only)
Enable Parity Error
Interrupt
Parity Error
Bits Used for Parity Control and Generation
The LSI53C825A implements a flexible parity scheme that allows control
of the parity sense, allows parity checking to be turned on or off, and has
the ability to deliberately send a byte with bad parity over the SCSI bus
to test parity error recovery procedures.
are involved in parity control and observation.
parity control function of the Enable Parity Checking and Assert SCSI
Even Parity bits in the
describes the options available when a parity error occurs.
PCI Cache Mode
Location
SCSI Control
Zero
Bit 1
SCSI Control
Zero
Bit 3
SCSI Control
One
Bit 2
SCSI Control
One
Bit 5
SCSI Interrupt
Enable Zero
(SIEN0), Bit 0
SCSI Interrupt
Status Zero
(SIST0), Bit 0
(SCNTL1),
(SCNTL1),
(SCNTL0),
(SCNTL0),
Description
Causes the LSI53C825A to automatically assert SATN/
when it detects a parity error while operating as an
initiator.
Enables the LSI53C825A to check for parity errors.
The LSI53C825A checks for odd parity.
Determines the SCSI parity sense generated by the
LSI53C825A to the SCSI bus.
Causes the LSI53C825A not to halt operations when a
parity error is detected in target mode.
Determines whether the LSI53C825A will generate an
interrupt when it detects a SCSI parity error.
This status bit is set whenever the LSI53C825A has
detected a parity error on the SCSI bus.
SCSI Control Zero (SCNTL0)
Table 2.3
Table 2.4
defines the bits that
register.
describes the
Table 2.5
2-21