LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 62

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.4.13.4 Masking
2-38
Some SCSI interrupts (indicated by the SIP bit in the ISTAT and one or
more bits in
One (SIST1)
in Initiator mode, only the Function Complete (CMP), Selected (SEL),
Reselected (RSL), General Purpose Timer Expired (GEN), and
Handshake-to-Handshake Timer Expired (HTH) interrupts are nonfatal.
When operating in Target mode CMP, SEL, RSL, Target mode: SATN/
active (M/A), GEN, and HTH are nonfatal. Refer to the description for the
Disable Halt on a Parity Error or SATN/ active (Target Mode Only) (DHP)
bit in the
behavior when the SATN/ interrupt is enabled during Target mode
operation. The Interrupt-on-the-Fly interrupt is also nonfatal, since
SCRIPTS can continue when it occurs.
The reason for nonfatal interrupts is to prevent SCRIPTS from stopping
when an interrupt occurs that does not require service from the CPU.
This prevents an interrupt when arbitration is complete (CMP set), when
the LSI53C825A has been selected or reselected (SEL or RSL set),
when the initiator has asserted ATN (target mode: SATN/ active), or when
the General Purpose or Handshake-to-Handshake timers expire. These
interrupts are not needed for events that occur during high-level
SCRIPTS operation.
Masking an interrupt means disabling or ignoring that interrupt. Interrupts
can be masked by clearing bits in the
(SIEN0)
registers or
How the chip responds to masked interrupts depends on: whether polling
or hardware interrupts are being used; whether the interrupt is fatal or
nonfatal; and whether the chip is operating in Initiator or Target mode.
If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS
do not stop, the appropriate bit in the SIST0 or SIST1 is still set, the SIP
bit in the ISTAT is not set, and the IRQ/ pin is not asserted. See
Section 2.4.13.3, “Fatal vs. Nonfatal Interrupts,”
interrupts.
Functional Description
and
SCSI Control One (SCNTL1)
DMA Interrupt Enable (DIEN)
SCSI Interrupt Status Zero (SIST0)
being set) are nonfatal. When the LSI53C825A is operating
SCSI Interrupt Enable One (SIEN1)
SCSI Interrupt Enable Zero
register to configure the chip’s
(for DMA interrupts) register.
or
for a list of the nonfatal
(for SCSI interrupts)
SCSI Interrupt Status