LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 133

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

SDP0L
MSG
C/D
I/O
Operating Registers
Latched SCSI Parity
This bit reflects the SCSI parity signal (SDP0/),
corresponding to the data latched in the
Latch
the least significant byte of the
(SIDL)
is set when the parity signal is active.
SCSI MSG/ Signal
SCSI C_D/ Signal
SCSI I_O/ Signal
These SCSI phase status bits are latched on the
asserting edge of SREQ/ when operating in either the
(SSTAT2 bit 4)
(SIDL). It changes when a new byte is latched into
FF4
register. This bit is active high, in other words, it
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
FF3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
FF2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
SCSI Input Data Latch
FF1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
FF0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
SCSI Input Data
Words in
the SCSI
Bytes or
FIFO
10
11
12
13
14
15
16
0
1
2
3
4
5
6
7
8
9
4-45
3
2
1
0