LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 63

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

If a fatal interrupt is masked and that condition occurs, then the SCRIPTS
still stop, the appropriate bit in the
DMA Status
(DSTAT),
SCSI Interrupt
Status Zero
(SIST0), or
SCSI Interrupt Status One (SIST1)
register is
set, and the SIP or DIP bit in the
Interrupt Status (ISTAT)
is set, but the
IRQ/ pin is not asserted.
When the chip is initialized, enable all fatal interrupts if you are using
hardware interrupts. If a fatal interrupt is disabled and that interrupt
condition occurs, the SCRIPTS halts and the system will never know it
unless it times out and checks the ISTAT after a certain period of
inactivity.
If you are polling the ISTAT instead of using hardware interrupts, then
masking a fatal interrupt will make no difference since the SIP and DIP
bits in the ISTAT inform the system of interrupts, not the IRQ/ pin.
Masking an interrupt after IRQ/ is asserted does not cause IRQ/ to be
deasserted.
2.4.13.5 Stacked Interrupts
The LSI53C825A stacks interrupts if they occur one after the other. If the
SIP or DIP bits in the
Interrupt Status (ISTAT)
register are set (first level),
then there is already at least one pending interrupt, and any future
interrupts are stacked in extra registers behind the
SCSI Interrupt Status
Zero
(SIST0),
SCSI Interrupt Status One
(SIST1), and
DMA Status
(DSTAT)
registers (second level). When two interrupts have occurred and
the two levels of the stack are full, any further interrupts set additional
bits in the extra registers behind
SCSI Interrupt Status Zero
(SIST0),
SCSI Interrupt Status One
(SIST1), and
DMA Status
(DSTAT). When the
first level of interrupts are cleared, all the interrupts that came in
afterward will move into the
SCSI Interrupt Status Zero
(SIST0),
SCSI
Interrupt Status One
(SIST1), and
DMA Status
(DSTAT). After the first
interrupt is cleared by reading the appropriate register, the IRQ/ pin is
deasserted for a minimum of three CLKs. The stacked interrupts move
into the SIST0, SIST1, or DSTAT and the IRQ/ pin is asserted once
again.
Since a masked nonfatal interrupt does not set the SIP or DIP bits,
interrupt stacking does not occur. A masked, nonfatal interrupt still posts
the interrupt in SIST0, but does not assert the IRQ/ pin. Since no
interrupt is generated, future interrupts move right into the SIST0 or
PCI Cache Mode
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