LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 166

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-78
Register: 0x44 (0xC4)
SCSI Longitudinal Parity (SLPAR)
Read/Write
SLPAR
Registers
7
x
x
SCSI Longitudinal Parity
The
of two multiplexed bytes; other register bit settings
determine what is displayed at this memory location at
any given time. When bit 5 in the
(SCNTL2)
the high and low bytes of the
(SLPAR)
which is displayed in the
(SLPAR)
Longitudinal Parity (SLPAR)
high byte or the low byte of the SLPAR word. The SLPAR
High Byte Enable bit,
determines which byte of the
(SLPAR)
ity (SLPAR)
cleared, the
contains the low byte of the SLPAR word; if it is set, the
SCSI Longitudinal Parity (SLPAR)
high byte of the SLPAR word.
This register performs a bytewise longitudinal parity
check on all SCSI data received or sent through the SCSI
core. If one of the bytes received or sent (usually the last)
is the set of correct even parity bits, SLPAR should go to
zero (assuming it started at zero). As an example,
suppose that the following three data bytes and one
check byte are received from the SCSI bus (all signals
are shown active HIGH):
SCSI Longitudinal Parity (SLPAR)
x
register. If the SLPMD bit is set, then the
register is visible on the
register together to give a single-byte value
(SLPMD) register is cleared, the chip XORs
register at any given time. If this bit is
SCSI Longitudinal Parity (SLPAR)
x
SLPAR
SCSI Control Two
x
SCSI Longitudinal Parity
register shows either the
SCSI Longitudinal Parity
SCSI Longitudinal Parity
x
SCSI Longitudinal Par-
SCSI Control Two
register contains the
register consists
(SCNTL2), bit 4,
x
register
SCSI
0
x
[7:0]