LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 96

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-8
Register: 0x0C
Cache Line Size
Read/Write
CLS
Register: 0x0D
Latency Timer
Read/Write
LT[7:0]
Registers
7
0
7
0
0
0
Cache Line Size
This register specifies the system cache line size in units
of 32-bit words. Cache mode is enabled and disabled by
the Cache Line Size Enable (CLSE) bit, bit 7 in the
Control (DCNTL)
LSI53C825A to align to cache line boundaries before
allowing any bursting, except during Memory Moves in
which the read and write addresses are not aligned to a
burst size boundary. For more information on this register,
see
Register.”
Latency Timer
The
clocks, the value of the Latency Timer for this PCI bus
master. The LSI53C825A supports this timer. All eight
bits are writable, allowing latency values of 0–255 PCI
clocks. Use the following equation to calculate an
optimum latency value for the LSI53C825A:
Latency = 2 + (Burst Size * (typical wait states +1)).
Values greater than optimum are also acceptable.
Section 2.1.3.1, “Support for PCI Cache Line Size
Latency Timer
0
0
0
0
register. Setting this bit causes the
CLS
register specifies, in units of PCI bus
LT
0
0
0
0
0
0
DMA
0
0
0
0
[7:0]
[7:0]