LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 137

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

SRST
SIGP
SEM
Operating Registers
2. Wait for an interrupt.
3. Read the
4. If the SCSI Interrupt Pending bit is set, then read the
5. If the SCSI Interrupt Pending bit is clear, and the DMA
6. Read the
Software Reset
Setting this bit resets the LSI53C825A. All operating
registers are cleared to their respective default values
and all SCSI signals are deasserted. Setting this bit does
not assert the SCSI RST/ signal. This reset does not
clear the ID Mode bit or any of the PCI configuration
registers. This bit is not self-clearing; it must be cleared
to clear the reset condition (a hardware reset also clears
this bit).
Signal Process
SIGP is a R/W bit that is writable at any time, and polled
and reset using
is used in various ways to pass a flag to or from a running
SCRIPTS instruction.
The only SCRIPTS instruction directly affected by the
SIGP bit is Wait For Selection/Reselection. Setting this bit
causes that instruction to jump to the alternate address
immediately. The instructions at the alternate jump
address should check the status of SIGP to determine
the cause of the jump. The SIGP bit is usable at any time
and is not restricted to the wait for selection/reselection
condition.
Semaphore
The SCRIPTS processor may set this bit using a
SCRIPTS register write instruction. An external processor
may also set it while the LSI53C825A is executing a
SCRIPTS operation. This bit enables the LSI53C825A to
SCSI Interrupt Status Zero (SIST0)
Status One (SIST1)
the SCSI Interrupt and go back to Step 2.
Interrupt Pending bit is set, then write 0x00 value to
this register.
aborted interrupt and to see if any other interrupting
conditions have occurred.
Interrupt Status (ISTAT)
DMA Status (DSTAT)
Chip Test Two
register to determine the cause of
(CTEST2). The SIGP bit
register to verify the
register.
or
SCSI Interrupt
4-49
6
5
4