LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 179

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x4F (0xCF)
SCSI Test Three (STEST3)
Read/Write
TE
STR
HSC
Operating Registers
TE
7
0
STR
6
0
TolerANT Enable
Setting this bit enables the active negation portion of
LSI Logic TolerANT technology. Active negation causes
the SCSI Request, Acknowledge, Data, and Parity
signals to be actively deasserted, instead of relying on
external pull-ups, when the LSI53C825A is driving these
signals. Active deassertion of these signals occurs only
when the LSI53C825A is in an information transfer
phase. When operating in a differential environment or at
Fast SCSI timings, TolerANT Active negation should be
enabled to improve setup and deassertion times. Active
negation is disabled after reset or when this bit is cleared.
For more information on LSI Logic TolerANT technology,
see
SCSI FIFO Test Read
Setting this bit places the SCSI core into a test mode in
which the SCSI FIFO is easily read. Reading the least
significant byte of the
register causes the FIFO to unload. The functions are
summarized in the following table.
Halt SCSI Clock
Asserting this bit causes the internal divided SCSI clock
to come to a stop in a glitchless manner. This bit is used
for test purposes or to lower I
mode.
Register
SODL0
SODL1
Name
SODL
Chapter 1, “Introduction.”
HSC
5
0
DSI
4
0
Operation
Register
Read
Read
Read
SCSI Output Data Latch (SODL)
S16
3
0
FIFO Bits
DD
[15:0]
[15:8]
[7:0]
TTM
during a power-down
2
0
CSF
FIFO Function
1
0
Unload
Unload
None
STW
0
0
4-91
7
6
5