LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 295

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

jump (Cont.)
L
last disconnect (LDSC)
latched SCSI parity
latency
load/store
lost arbitration (LOA)
LSI53C700 family compatibility (COM)
M
MAD bus programming
manual start mode (MAN)
master
max SCSI synchronous offset (MO[4:0])
max_lat (ML[7:0])
maximum stress ratings
memory
memory access control (MACNTL)
min_gnt (MG[7:0])
move to/from SFBR cycles
N
next_item_ptr (NIP[7:0])
no flush
O
opcode
operating conditions
operating registers
operator
P
parity
PCI
PCI commands
PCI configuration registers
call a relative address
call an absolute address
if true/false
instruction
(SDP0L)
for SD[15:8] (SPL1)
timer (LT[7:0])
MAD[3:1]
control for set or reset pulses (MASR)
data parity error (MDPE)
enable (ME)
parity error enable (MPEE)
I/O address/DSA offset
move instructions
store instruction only
general information
error
and external memory interface timing diagrams
base address one (memory)
base address zero (I/O)
class code
command
(PAR)
5-9
5-37
5-26
5-41
,
4-45
5-14
3-17
4-3
4-75
5-29
4-7
5-35
2-2
4-80
,
4-14
4-8
4-13
5-26
6-2
4-44
5-36
4-47
4-18
4-47
,
6-2
4-15
5-41
5-29
5-34
4-66
4-1
5-42
5-27
Index
4-9
5-34
4-41
4-58
4-9
,
4-79
4-67
4-70
4-34
4-59
6-13
PCI configuration space
PCI I/O space
PCI memory space
prefetch
R
read
read/write
register
register addresses
relative
relative addressing mode
reselect
reselected (RSL)
Reserved
reset
response ID zero (RESPID0)
return instruction
S
scratch
scratcha/b operation (SRTCH)
SCRIPTS
SCRIPTS processor
device ID
expansion ROM base address
header type
interrupt line
interrupt pin
latency timer
max_lat
min_gnt
revision ID
status
vendor ID
enable (PFEN)
flush (PFF)
modify-write cycles
write instructions
write system memory from SCRIPTS
instructions
system memory from SCRIPTS
address
address - A[6:0]
PCI configuration registers
instruction
input
SCSI offset (ROF)
byte register (SBR)
register A (SCRATCHA)
register B (SCRATCHB)
registers C–R (SCRATCHC–SCRATCHR)
interrupt instruction received (SIR)
performance
0x02
0x04
0x06
0x08
0x09
0x0D
0x0E
0x10
0x3D
0x3E
0x3F
5-21
6-12
4-80
4-5
4-14
4-13
5-41
4-3
4-3
4-5
4-7
4-7
4-9
4-14
4-9
4-13
4-8
4-13
4-3
4-3
5-15
2-2
4-7
4-68
5-24
4-9
4-13
4-13
2-11
4-8
4-71
5-32
4-68
2-2
,
5-26
2-11
5-24
,
5-27
4-88
5-26
4-68
4-74
2-1
5-19
4-64
4-94
4-85
,
4-53
5-33
4-11
5-38
4-41
5-38
,
4-67
4-94
IX-5