EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 317

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 1–4. Enhanced PLL Signals
Notes to
(1)
(2)
(3)
Altera Corporation
July 2005
(1)
(2)
(2)
(2)
This input pin is shared by all enhanced and fast PLLs.
These are either single-ended or differential pins.
EP1S10, EP1S20, and EP1S25 devices in 672-pin ball grid array (BGA) and 484- and 672-pin FineLine BGA packages
only have two pairs of external clocks (i.e., pll_out0p, pll_out0n, pll_out1p, and pll_out1n).
Figure
1–4:
pllenable
inclk0
inclk1
areset
clkswitch
scanclk
scandata
scanaclr
clkena[5..0]
pfdena
extclkena[3..0]
Figure 1–4
shows all the possible ports of the enhanced PLLs.
active_clock
scandataout
clkbad[1..0]
pll_out0p
pll_out0n
pll_out1p
pll_out1n
pll_out2p
pll_out2n
pll_out3p
pll_out3n
clk[5..0]
extclk4
clkloss
locked
General-Purpose PLLs in Stratix & Stratix GX Devices
(3)
(3)
(3)
(3)
Stratix Device Handbook, Volume 2
Only PLLs
11 and 12
Only PLLs
5 and 6
Signal Driven by Internal Logic
Signal Driven to Internal Logic
Internal Clock Signal
Physical Pin
1–7