EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 461

IC STRATIX FPGA 80K LE 956-BGA

EP1S80B956C7N

Manufacturer Part Number
EP1S80B956C7N
Description
IC STRATIX FPGA 80K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S80B956C7N

Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S80B956C7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S80B956C7N
Manufacturer:
ALTERA
0
Altera Corporation
June 2006
Thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up
Non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA
Thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up
Non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA
Table 4–9. Bidirectional pad Limitation Formulas (Where VREF Inputs Exist)
Table 4–10. Bidirectional Pad Limitation Formulas (Where VREF Outputs Exist)
Package Type
Package Type
The previous equation accounts for the input limitations, but you must
apply the appropriate equation from
limitations.
When at least one additional output exists but no voltage referenced
inputs exist, apply the appropriate formula from
When additional voltage referenced inputs and other outputs exist in the
same VREF bank, then the bidirectional pad limitation must again
simultaneously adhere to the input and output limitations. See the
following equation.
<Total number of bidirectional pads> + <Total number of input pads> 40 (20 on
each side of the VREF pad)
<Total number of bidirectional pads> 20 (per
<Total number of bidirectional pads> 15 (per
<Total number of bidirectional pads> + <Total number of additional
output pads> – <Total number of pads from the smallest group of pads
controlled by an OE> 20 (per
<Total number of bidirectional pads> + <Total number of additional
output pads> – <Total number of pads from the smallest group of pads
controlled by an OE> 15 (per
Selectable I/O Standards in Stratix & Stratix GX Devices
Formula
Formula
VREF
VREF
Table 4–9
Stratix Device Handbook, Volume 2
pad)
pad)
to determine the output
Table
VREF
VREF
4–10.
pad)
pad)
4–33

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