EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 746

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Configuration Schemes
Figure 11–13. Parallel Data Transfer in Serial Configuration with a Microprocessor
Note to
(1)
Figure 11–14. Multiple Device Parallel Configuration with the Same Data Using a Microprocessor
Notes to
(1)
(2)
11–28
Stratix Device Handbook, Volume 2
Microprocessor
You should connect the pull-up resistors to any V
specification.
You should connect the pull-up resistors to any V
specification.
The nCEO pins are left unconnected when configuring the same data into multiple Stratix or Stratix GX devices.
ADDR DATA[7..0]
Figure
Microprocessor
Figure
Memory
ADDR DATA[7..0]
Memory
11–13:
11–14:
f
For more information on configuring multiple Altera devices in the same
configuration chain, see the Configuring Mixed Altera FPGA Chains
chapter in the Configuration Handbook, Volume 2.
V
CC
V
10 kΩ
CC
(1)
10 kΩ
(1)
V
CC
GND
V
CC
GND
10 kΩ
(1)
10 kΩ
(1)
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
CC
CC
Stratix Device
Stratix Device
that meets the Stratix high-level input voltage (V
that meets the Stratix high-level input voltage (V
MSEL2
MSEL1
MSEL0
MSEL2
MSEL1
MSEL0
nCEO
nCEO
GND
N.C. (2)
GND
GND
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Stratix Device
Stratix Device
Altera Corporation
MSEL2
MSEL1
MSEL0
nCEO
MSEL2
MSEL1
MSEL0
nCEO
IH
IH
)
)
July 2005
GND
N.C.
N.C. (2)
GND