EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 360

IC STRATIX FPGA 80K LE 956-BGA

EP1S80B956C7N

Manufacturer Part Number
EP1S80B956C7N
Description
IC STRATIX FPGA 80K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S80B956C7N

Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

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Quantity
Price
Part Number:
EP1S80B956C7N
Manufacturer:
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Quantity:
10 000
Part Number:
EP1S80B956C7N
Manufacturer:
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0
Board Layout
Board Layout
1–50
Stratix Device Handbook, Volume 2
The enhanced and fast PLL circuits in Stratix and Stratix GX devices
contain analog components embedded in a digital device. These analog
components have separate power and ground pins to minimize noise
generated by the digital components. Both Stratix and Stratix GX
enhanced and fast PLLs use separate VCC and ground pins to isolate
circuitry and improve noise resistance.
VCCA & GNDA
Each enhanced and fast PLL uses separate VCC and ground pin pairs for
their analog circuitry. The analog circuit power and ground pin for each
PLL is called PLL<PLL number>_VCCA and PLL<PLL number>_GNDA.
Connect the VCCA power pin to a 1.5-V power supply, even if you do not
use the PLL. Isolate the power connected to VCCA from the power to the
rest of the Stratix and Stratix GX device or any other digital device on the
board. You can use one of three different methods of isolating the VCCA
pin: separate V
V
Separate V
A mixed signal system is already partitioned into analog and digital
sections, each with its own power planes on the board. To isolate the
VCCA pin using a separate V
analog 1.5-V power plane.
Partitioned V
Fully digital systems do not have a separate analog power plane on the
board. Because it is expensive to add new planes to the board, you can
create islands for VCCA_PLL.
with an analog power island. The dielectric boundary that creates the
island should be 25 mils thick.
within V
CCINT
plane, and thick V
CCINT
CCA
CCA
Power Plane
for V
CCA
Island within V
power planes, a partitioned V
CCA
.
CCA
CCA
Figure 1–23
traces.
Figure 1–23
CCINT
power plane, connect the VCCA pin to the
Plane
shows an example board layout
shows a partitioned plane
CCA
island within the
Altera Corporation
July 2005

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