EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 603
EP1S80B956C7N
Manufacturer Part Number
EP1S80B956C7N
Description
IC STRATIX FPGA 80K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S80B956C7N
Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–14. Block Diagram Representation of Decimation
Decimation filters reverse the effect of the interpolation filters. Before the
decimation process, a low pass filter is applied to the signal to attenuate
noise and aliases present beyond the Nyquist frequency. The filtered
signal is then applied to the decimation filter, which processes every D-th
input. Therefore the values between samples D, D-1, D-2 etc. are ignored.
This allows the filter to run M times slower than the input data rate.
In a typical system, after the analog to digital conversion is complete, the
data needs to be filtered to remove aliases inherent in the sampled data.
Further, at this point there is no need to continue to process this data at
the higher sample (oversampled) rate. Therefore, a decimation FIR filter
at the output of the ADC lowers the data rate to a value that can be
processed digitally.
Figure 7–15
is decimated by a factor of 4 to 2 MHz. The Nyquist frequency of the
downsampled signal must be greater than 2 MHz, and is chosen to be
2.25 MHz in this example.
sample rate f s
shows a specific example where a signal spread over 8 MHz
Input
LPF
Stratix Device Handbook, Volume 2
D
Output
sample rate f s /D
7–25
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