EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 318
EP1S80B956C7N
Manufacturer Part Number
EP1S80B956C7N
Description
IC STRATIX FPGA 80K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S80B956C7N
Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Enhanced PLLs
1–8
Stratix Device Handbook, Volume 2
inclk[1..0]
fbin
pllena
clkswitch
areset
clkena[5..0]
extclkena[3..0]
pfdena
scanclk
scandata
scanaclr
Table 1–4. Enhanced PLL Input Signals
Port
Primary and secondary reference clock inputs to
PLL
External feedback input to the PLL (PLLs 5 and 6
only)
Enable pin for enabling or disabling all or a set of
PLLs active high
Switchover signal used to initiate external clock
switchover control this signal switches the clock
on the rising edge of clkswitch
Signal used to reset the PLL which re-
synchronizes all the counter outputs active high
Enable clock driving regional or global
clock active high
Enable clock driving external clock (PLLs 5 and 6
only) active high
Enables the outputs from the phase frequency
detector active high
Serial clock signal for the real-time PLL control
feature
Serial input data stream for the real-time PLL
control feature
Serial shift register reset clearing all registers in
the serial shift chain active high
Tables 1–4
and
Description
1–5
describe all the enhanced PLL ports.
Pin
Pin
Pin
Logic array
Logic array
Logic array
Logic array
Logic array
Logic array
Logic array
Logic array
Source
Altera Corporation
×n counter
Phase frequency
detector (PFD)
General PLL
control signal
PLL switchover
circuit
General PLL
control signal
Clock output
Clock output
PFD
Reconfiguration
circuit
Reconfiguration
circuit
Reconfiguration
circuit
Destination
July 2005
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