EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 100
EZ80F920120MOD
Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog
Datasheets
1.EZ80F920120MOD.pdf
(269 pages)
2.EZ80F920120MOD.pdf
(4 pages)
3.EZ80F920120MOD.pdf
(2 pages)
Specifications of EZ80F920120MOD
Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
EZ80F920120MOD
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PS015308-0404
Note:
Timer Reload Register—High Byte
The Timer Reload Register—High Byte, detailed in Timer Reload Register—High Byte
(TMR0_RR_H = 0082h, TMR1_RR_H = 0085h, TMR2_RR_H = 0088h, TMR3_RR_H =
008Bh, TMR4_RR_H = 008Eh, or TMR5_RR_H = 0091h), stores the most-significant
byte (MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload
value is reloaded into the timer upon end-of-count. When RST_EN (TMRx_CTL[1]) is set
to 1 to enable the automatic reload and restart function, the timer reload value is written to
the timer on the next rising edge of the clock.
Table 37. Timer Reload Register—High Byte
(TMR0_RR_H = 0082h, TMR1_RR_H = 0085h, TMR2_RR_H = 0088h,
TMR3_RR_H = 008Bh, TMR4_RR_H = 008Eh, or TMR5_RR_H = 0091h)
Timer Input Source Select Register
The Timer Input Source Select register, detailed in Timer Input Source Select Register
(TMR_ISS = 0092h), sets the input source for Programmable Reload Timer 0–3 (TMR0,
TMR1, TMR2, TMR3). Event frequency must be less than one-half of the system clock
frequency. When configured for event inputs through the port pins, the Timers decrement
on the fifth system clock rising edge following the rising edge of the port pin.
Bit
Reset
CPU Access
Note: W = Write only.
Bit
Position
[7:0]
TMRx_RR_H
The Timer Data registers and Timer Reload registers share the same address space.
Value
00h–FFh These bits represent the High byte of the 2-byte timer
W
P R E L I M I N A R Y
7
0
Description
reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7
is bit 15 (msb) of the 16-bit timer reload value. Bit 0 is bit 8
of the 16-bit timer reload value.
W
6
0
W
5
0
W
4
0
W
3
0
Programmable Reload Timers
Product Specification
W
2
0
eZ80F92/eZ80F93
W
1
0
W
0
0
88
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