EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 163

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Table 82. I
If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address
plus the Write bit. The master then issues a restart followed by the first part of the 10-bit
address again, but with the Read bit. The status code then becomes
responsibility of the slave to remember that it had been selected prior to the restart.
If a repeated START condition is received, the status code is
After each data byte is received, the IFLG is set and one of the status codes listed in I
Master Receive Status Codes For Data Bytes is in the I2C_SR register.
Code
48h
38h
68h
78h
B0h
R = Read bit; that is, the lsb is set to 1.
2
I
Addr + R
transmitted, ACK
not received
Arbitration lost
Arbitration lost,
SLA+W received,
ACK transmitted
Arbitration lost,
General call addr
received, ACK
transmitted
Arbitration lost,
SLA+R received,
ACK transmitted
C Master Receive Status Codes
2
C State
P R E L I M I N A R Y
Microcontroller Response Next I
For a 7-bit address:
Set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP,
clear IFLG
For a 10-bit address:
Write extended address
byte to DATA, clear IFLG
Clear IFLG
Or set STA, clear IFLG
Clear IFLG, clear AAK = 0
Or clear IFLG, set AAK = 1 Receive data byte,
Same as code 68h
Write byte to DATA,
clear IFLG, clear AAK = 0
Or write byte to DATA,
clear IFLG, set AAK = 1
10h
Transmit repeated
START
Transmit STOP
Transmit STOP then
START
Transmit extended
address byte
Return to idle
Transmit START when
bus is free
Receive data byte,
transmit NACK
transmit ACK
Same as code 68h
Transmit last byte,
receive ACK
Transmit data byte,
receive ACK
Product Specification
instead of
40h
I2C Serial I/O Interface
eZ80F92/eZ80F93
2
C Action
or
48h
08h
. It is the
.
2
C
151