EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 146
EZ80F920120MOD
Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog
Datasheets
1.EZ80F920120MOD.pdf
(269 pages)
2.EZ80F920120MOD.pdf
(4 pages)
3.EZ80F920120MOD.pdf
(2 pages)
Specifications of EZ80F920120MOD
Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
EZ80F920120MOD
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Figure 30.SPI Timing
PS015308-0404
(CPHA bit = 0) Data Out
(CPHA bit = 1) Data Out
ENABLE (To Slave)
SCK (CPOL bit = 0)
SCK (CPOL bit = 1)
Sample Input
Sample Input
ated by the master, the SCK pin becomes an input on a slave device. The SPI contains an
internal divide-by-two clock divider. In MASTER mode, the SPI serial clock is one-half
the frequency of the clock signal created by the SPI’s Baud Rate Generator.
As demonstrated in Figure 30 and SPI Clock Phase and Clock Polarity Operation, four
possible timing relations may be chosen by using control bits CPOL and CPHA in the SPI
Control register. See the SPI Control Register (SPI_CTL) on page 139. Both the master
and slave must operate with the identical timing, clock polarity (CPOL), and clock phase
(CPHA). The master device always places data on the MOSI line a half-cycle before the
clock edge (SCK signal) so that the slave device latches the data.
Table 72. SPI Clock Phase and Clock Polarity Operation
CPHA
0
0
1
1
CPOL
MSB
0
1
0
1
MSB
1
6
P R E L I M I N A R Y
Transmit
Falling
Falling
Rising
Rising
Edge
6
SCK
2
Number of Cycles on the SCK Signal
5
5
3
4
Receive
Falling
Falling
Rising
Rising
4
Edge
4
SCK
3
3
5
2
State
SCK
High
High
Low
Low
Idle
2
6
Product Specification
1
Serial Peripheral Interface
1
7
eZ80F92/eZ80F93
LSB
Characters?
LSB
Between
SS High
8
Yes
Yes
No
No
134
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