EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 135

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Bit
Position
5
THRE
4
BI
3
FE
2
PE
1
OE
Value
0
1
0
1
0
1
0
1
0
1
Description
Transmit holding register/FIFO is not empty.
Transmit holding register/FIFO is empty. This bit cannot be
set to 1 during the BREAK condition. This bit only becomes 1
after the BREAK command is removed.
Receiver does not detect a BREAK condition. This bit is reset
to 0 when the UARTx_LSR register is read.
Receiver detects a BREAK condition on the receive input line.
This bit is 1 if the duration of BREAK condition on the receive
data is longer than one character transmission time, the time
depends on the programming of the UARTx_LSR register. In
case of FIFO only one null character is loaded into the
receiver FIFO with the framing error. The framing error is
revealed to the CPU whenever that particular data is read
from the receiver FIFO.
No framing error detected for character at the top of the FIFO.
This bit is reset to 0 when the UARTx_LSR register is read.
Framing error detected for the character at the top of the
FIFO. This bit is set to 1 when the stop bit following the data/
parity bit is logic 0.
The received character at the top of the FIFO does not
contain a parity error. In multidrop mode, this indicates that
the received character is a data byte. This bit is reset to 0
when the UARTx_LSR register is read.
The received character at the top of the FIFO contains a parity
error. In multidrop mode, this indicates that the received
character is an address byte.
The received character at the top of the FIFO does not
contain an overrun error. This bit is reset to 0 when the
UARTx_LSR register is read.
Overrun error is detected. If the FIFO is not enabled, this
indicates that the data in the receive buffer register was not
read before the next character was transferred into the
receiver buffer register. If the FIFO is enabled, this indicates
the FIFO was already full when an additional character was
received by the receiver shift register. The character in the
receiver shift register is not put into the receiver FIFO.
P R E L I M I N A R Y
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80F92/eZ80F93
123