EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 199

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
ZDI Bus Status Register
The ZDI Bus Status register monitors BUSACKs during ZDI DEBUG mode. See ZDI Bus
Control Register (ZDI_BUS_STAT = 17h in the ZDI Register Read Only Address Space).
Table 109. ZDI Bus Control Register
(ZDI_BUS_STAT = 17h in the ZDI Register Read Only Address Space)
ZDI Read Memory Register
When a Read is executed from the ZDI Read Memory register, the eZ80F92 device fetches
the data from the memory address currently pointed to by the program counter, PC; the
program counter is then incremented. In Z80 MEMORY mode, the memory address is
{MBASE, PC[15:0]}. In ADL MEMORY mode, the memory address is PC[23:0]. Refer
to the eZ80 CPU User Manual (UM0077) for more information regarding Z80 and ADL
MEMORY modes. The program counter, PC, increments after each data Read. However,
the ZDI register address does not increment automatically when this register is accessed.
As a result, the ZDI master can read any number of data bytes out of memory through the
ZDI Read Memory register. See ZDI Read Memory Register (ZDI_RD_MEM = 20h in
the ZDI Register Read Only Address Space).
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
ZDI_BUSACK_EN
6
ZDI_BUS_STAT
[5:0]
Value
0
1
0
1
000000
P R E L I M I N A R Y
R
7
0
Description
Bus requests by external peripherals using the
BUSREQ pin are ignored. The bus acknowledge
signal, BUSACK, is not asserted.
Bus requests by external peripherals using the
BUSREQ pin are accepted. A bus acknowledge occurs
at the end of the current ZDI operation. The bus
acknowledge is indicated by asserting the BUSACK
pin.
Address and data buses are not relinquished to an
external peripheral. bus acknowledge is deasserted
(BUSACK pin is High).
Address and data buses are relinquished to an external
peripheral. bus acknowledge is asserted (BUSACK pin
is Low).
Reserved.
R
6
0
R
5
0
R
4
0
R
3
0
Product Specification
R
ZiLOG Debug Interface
2
0
eZ80F92/eZ80F93
R
1
0
R
0
0
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