EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 152

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
SPI Status Register
The SPI Status Read Only register returns the status of data transmitted using the serial
peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to a logical 0. See
SPI Status Register (SPI_SR = 00BBh).
Table 76. SPI Status Register (SPI_SR = 00BBh)
Bit
Position
2
CPHA
[1:0]
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
SPIF
6
WCOL
5
4
MODF
[3:0]
Value Description
0
1
00
Value Description
0
1
0
1
0
0
1
0000
SS must go High after transfer of every byte of data.
SS can remain Low to transfer any number of data bytes.
Reserved.
SPI data transfer is not finished.
SPI data transfer is finished. If enabled, an interrupt is
generated. This bit flag is cleared to 0 by a Read of the
SPI_SR register.
An SPI write collision is not detected.
An SPI write collision is detected. This bit flag is cleared to 0
by a Read of the SPI_SR registers.
Reserved.
A mode fault (multimaster conflict) is not detected.
A mode fault (multimaster conflict) is detected. This bit flag is
cleared to 0 by a Read of the SPI_SR register.
Reserved.
P R E L I M I N A R Y
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
Product Specification
Serial Peripheral Interface
R
2
0
eZ80F92/eZ80F93
R
1
0
R
0
0
140