EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 155

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Data Validity
The data on the SDA line must be stable during the High period of the clock. The High or
Low state of the data line can only change when the clock signal on the SCL line is Low as
illustrated in Figure 31.
Figure 31.I
START and STOP Conditions
Within the I
STOP conditions. See Figure 32. A High-to-Low transition on the SDA line while SCL is
High indicates a START condition. A Low-to-High transition on the SDA line while SCL
is High defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to
be busy after the START condition. The bus is considered to be free a defined time after
the STOP condition.
Figure 32.START and STOP Conditions In I
SDA Signal
SDA Signal
SCL Signal
SCL Signal
2
2
C Clock and Data Relationship
C bus protocol, unique situations arise which are defined as START and
START Condition
S
Data Valid
Data Line
Stable
P R E L I M I N A R Y
Data Allowed
Change of
2
C Protocol
Product Specification
STOP Condition
I2C Serial I/O Interface
eZ80F92/eZ80F93
P
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