EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 88

MODULE EZ80F92 512K 20MHZ

EZ80F920120MOD

Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog

Specifications of EZ80F920120MOD

Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
PS015308-0404
Watch-Dog Timer Registers
If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the WDT
asserts an NMI for CPU processing. The NMI_FLAG bit can be polled by the CPU to
determine the source of the NMI event.
Watch-Dog Timer Control Register
The Watch-Dog Timer Control register, detailed in Watch-Dog Timer Control Register, is
an 8-bit Read/Write register used to enable the Watch-Dog Timer, set the time-out period,
indicate the source of the most recent RESET, and select the required operation upon
WDT time-out.
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
WDT_EN
6
NMI_OUT
5
RST_FLAG*
[4:3]
WDT_CLK
Note: *RST_FLAG is only cleared by a non-WDT RESET.
Value Description
0
1
0
1
0
1
00
01
10
11
Table 27. Watch-Dog Timer Control Register
R/W
WDT is disabled.
WDT is enabled. When enabled, the WDT cannot be disabled
without a
WDT time-out resets the CPU.
WDT time-out generates a nonmaskable interrupt (NMI) to the
CPU.
RESET caused by external full-chip reset or ZDI reset.
RESET caused by WDT time-out. This flag is set by the WDT
time-out, even if the NMI_OUT flag is set to 1. The CPU can
poll this bit to determine the source of the RESET or NMI.
WDT clock source is system clock.
WDT clock source is Real-Time Clock source (32 KHz on-chip
oscillator or 50/60Hz input as set by RTC_CTRL[4]).
Reserved.
Reserved.
P R E L I M I N A R Y
7
0
(WDT_CTL = 0093h)
R/W
6
0
RESET
0/1
.
R
5
R/W
4
0
R/W
3
0
Product Specification
R
2
0
eZ80F92/eZ80F93
Watch-Dog Timer
R/W
1
0
R/W
0
0
76

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