EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 142

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Table 70. GPIO Mode Selection when using the IrDA Encoder/Decoder
PS015308-0404
GPIO Port D Bits
PD0
PD1
PD2–PD7
Jitter
Infrared Encoder/Decoder Signal Pins
Loopback Testing
Setting the upper 4 bits of IR_CTL to
receiver. In this mode, the IrDA receiver uses edge detection on the IR_RxD bit stream.
Due to the inherent sampling of the received IR_RxD signal by the BIt Rate Clock, some
jitter can be expected on the first bit in any sequence of data. However, all subsequent bits
in the received data stream are a fixed 16 clock periods wide.
The IrDA endec signal pins (IR_TxD and IR_RxD) are multiplexed with General-Purpose
I/O (GPIO) pins. These GPIO pins must be configured for alternate function operation for
the endec to operate.
The remaining six UART0 pins (CTS0, DCD0, DSR0, DTR0, RTS and RI0) are not
required for use with the endec. The UART0 modem status interrupt should be disabled to
prevent unwanted interrupts from these pins. The GPIO pins corresponding to these six
unused UART0 pins can be used for inputs, outputs, or interrupt sources. Recommended
GPIO Port D control register settings are provided in GPIO Mode Selection when using
the IrDA Encoder/Decoder. Refer to the General-Purpose Input/Output section on page 41
for additional information on setting the GPIO Port modes.
Both internal and external loopback testing can be accomplished with the IrDA endec on
the eZ80F92 device. Setting the LOOP_BACK bit to 1 enables internal loopback testing.
During internal loopback, the IR_TxD output signal is inverted and connected on-chip to
the IR_RxD input. External loopback testing of the off-chip IrDA transceiver can be
accomplished by transmitting data from the UART while the receiver is enabled
(IR_RxEN set to 1).
Allowable GPIO
Port Mode
7
7
Any other than GPIO Mode 7
(1, 2, 3, 4, 5, 6, 8, or 9)
P R E L I M I N A R Y
00h
Allowable Port Mode Functions
Alternate function.
Alternate function.
Output, input, open-drain, open-source, level-
sensitive interrupt input, or edge-triggered
interrupt input.
disables the frequency divider but not the IrDA
Product Specification
Infrared Encoder/Decoder
eZ80F92/eZ80F93
130