EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 178

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

eZ80F92/eZ80F93
Product Specification
166
ZDI Data Out
ZDI Data Out
(Read)
(Read)
ZCL
ZDA
Start Signal
Figure 39.ZDI Read Timing
ZDI Single-Bit Byte Separator
Following each 8-bit ZDI data transfer, a single-bit byte separator is used. To initiate a new
ZDI command, the single-bit byte separator must be High (logical 1) to allow for a new
ZDI START command to be sent. For all other cases, the single-bit byte separator can be
either Low (logical 0) or High (logical 1). When ZDI is configured to allow the CPU to
accept external bus requests, the single-bit byte separator should be Low (logical 0) during
all ZDI commands. This Low value indicates that ZDI is still operating and is not ready to
relinquish the Bus. The CPU does not accept the external bus requests until the single-bit
byte separator is a High (logical 1). For more information on accepting bus requests in
ZDI DEBUG mode, please see the Bus Requests During ZDI DEBUG Mode section on
page 170.
ZDI Register Addressing
Following a START signal the ZDI master must output the ZDI register address. All data
transfers with the ZDI block use special ZDI registers. The ZDI control registers that
reside in the ZDI register address space should not be confused with the eZ80F92 device
peripheral registers that reside in the I/O address space.
Many locations in the ZDI control register address space are shared by two registers, one
for Read Only access and one for Write Only access. As an example, a Read from ZDI
register address
returns the eZ80 Product ID Low Byte while a Write to this same
00h
location,
, stores the Low byte of one of the address match values used for generating
00h
BREAK points.
The format for a ZDI address is seven bits of address, followed by one bit for Read or
Write control, and completed by a single-bit byte separator. The ZDI executes a Read or
Write operation depending on the state of the R/W bit (0 = Write, 1 = Read). If no new
START command is issued at completion of the Read or Write operation, the operation
PS015308-0404
P R E L I M I N A R Y
ZiLOG Debug Interface