EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 162

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Table 81. I
When all bytes are transmitted, the microcontroller should write a 1 to the STP bit in the
I2C_CTL register. The I
to the idle state.
Master Receive
In MASTER RECEIVE mode, the I
After the START condition is transmitted, the IFLG bit is 1 and the status code
loaded in the I2C_SR register. The I2C_DR register should be loaded with the slave
address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a Read.
The IFLG bit should be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit are
transmitted, the IFLG bit is set and one of the status codes listed in I
Status Codes is in the I2C_SR register.
Table 82. I
Code I
30h
38h
Code
40h
R = Read bit; that is, the lsb is set to 1.
Data byte
transmitted,
ACK not received
Arbitration lost
2
C State
2
2
I
Addr + R
transmitted, ACK
received
C Master Transmit Status Codes For Data Bytes (Continued)
C Master Receive Status Codes
2
C State
2
C then transmits a STOP condition, clears the STP bit and returns
P R E L I M I N A R Y
Microcontroller Response Next I
Same as code 28h
Clear IFLG
Or set STA, clear IFLG
Microcontroller Response Next I
For a 7-bit address,
clear IFLG, AAK = 0
Or clear IFLG, AAK = 1
For a 10-bit address
Write extended address
byte to DATA, clear IFLG
2
C receives a number of bytes from a slave transmitter.
Same as code 28h
Return to idle
Transmit START when bus
free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit extended
address byte
Product Specification
2
C Action
2
I2C Serial I/O Interface
eZ80F92/eZ80F93
C Master Receive
2
C Action
08h
is
150