EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 50

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Clock Peripheral Power-Down Registers
Caution:
•
•
•
•
The CPU can be brought out of HALT mode by any of the following operations:
•
•
•
•
•
To minimize current in HALT mode, the system clock should be disabled for all unused
on-chip peripherals via the Clock Peripheral Power-Down Registers.
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to
be disabled unused on-chip peripherals. Upon RESET, all peripherals are enabled. The
clock to unused peripherals can be disabled by setting the appropriate bit in the Clock
Peripheral Power-Down Registers to 1. When powered down, the peripherals are com-
pletely disabled. To reenable, the bit in the Clock Peripheral Power-Down Registers must
be cleared to 0.
Many peripherals feature separate enable/disable control bits that must be appropriately
set for operation. These peripheral specific enable/disable bits do not provide the same
level of power reduction as the Clock Peripheral Power-Down Registers. When powered
down, the standard peripheral control registers are not accessible for Read or Write access.
See Tables 4 and 5.
Primary crystal oscillator is enabled and continues to operate
The system clock is enabled and continues to operate
The CPU is idle
The Program Counter (PC) stops incrementing
A nonmaskable interrupt (NMI)
A maskable interrupt
A RESET via the external RESET pin driven Low
A Watch-Dog Timer time-out (if configured to generate either an NMI or RESET
upon time-out)
A RESET via execution of a Debug RESET command
During HALT mode, the CPU freezes the last address and drives the address bus
with this value. The GPIO Ports remain as configured by the user. Prior to enter-
ing HALT mode, the data bus is driven Low and the control signals MREQ,
CS3:0, INSTRD, BUSACK, IOREQ, RD, and WR are driven High.
P R E L I M I N A R Y
Product Specification
eZ80F92/eZ80F93
Low-Power Modes
38