EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 81

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Chip Select Registers
Chip Select x Lower Bound Register
For Memory Chip Selects, the Chip Select x Lower Bound register, detailed in Chip Select
x Lower Bound Register (CS0_LBR = 00A8h, CS1_LBR = 00ABh, CS2_LBR = 00AEh,
CS3_LBR = 00B1h), defines the lower bound of the address range for which the corre-
sponding Memory Chip Select (if enabled) can be active. For I/O Chip Selects, this regis-
ter defines the address to which ADDR[15:8] is compared to generate an I/O Chip Select.
All Chip Select lower bound registers reset to
Table 22. Chip Select x Lower Bound Register
(CS0_LBR = 00A8h, CS1_LBR = 00ABh, CS2_LBR = 00AEh, CS3_LBR = 00B1h)
Bit
CS0_LBR Reset
CS1_LBR Reset
CS2_LBR Reset
CS3_LBR Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
CSx_LBR
Value Description
00h–
FFh
For Memory Chip Selects (
This byte specifies the lower bound of the Chip Select address
range. The upper byte of the address bus, ADDR[23:16], is
compared to the values contained in these registers for
determining whether a Memory Chip Select signal should be
generated.
For I/O Chip Selects (
This byte specifies the Chip Select address value. ADDR[15:8] is
compared to the values contained in these registers for
determining whether an I/O Chip Select signal should be
generated.
R/W
P R E L I M I N A R Y
7
0
0
0
0
R/W
6
0
0
0
0
R/W
5
0
0
0
0
00h
CSX_IO
.
R/W
4
0
0
0
0
CSX_IO
= 1)
R/W
3
0
0
0
0
= 0)
Chip Selects and Wait States
Product Specification
R/W
2
0
0
0
0
eZ80F92/eZ80F93
R/W
1
0
0
0
0
R/W
0
0
0
0
0
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