SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 12

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

3.16
The Mailbox and DMA protocol use the same data latching and steering logic, so it is important to note that in a system where
both mechanisms are used, the system designer must be careful to ensure that one type of transfer is finished before the next is
started. Setting bits 1 and 2 to ‘1’ in register 0xC006 enables the Mailbox/DMA interface. All transfers to and from the Data
Registers are made through GPIO 0 to 15. Data written into the SL11R is latched into a 16-bit register on the rising edge of nWR
(GPIO 17) when ADDR (GPIO 19) is high and nCS (GPIO 18) is low. Data is read out of the SL11R by asserting nRD (GPIO 16)
low while ADDR (GPIO 19) is high and nCS (GPIO 18) is low. This also applies when data is written or read during DMA transfers.
A functional logic diagram is shown in Figure 3-2.
3.17
The mailbox interface is accessed through three registers:
When data is transferred to the Sl11R through the Mailbox Interface, the external system must perform the transfer based on the
values in the status register. When a word is written to the SL11R, the ‘IF’ (INBUFF FULL) bit in the status register (0xC0C2) is
set by the SL11R hardware. This bit must be polled until it is cleared to ‘0’ by the SL11R. This indicates that the word has been
accepted by the SL11R and that it is ready for another word. When data is read from the SL11R, the ‘OF’ (OUTBUFF FULL) bit
in the status register will be set by the SL11R when valid data is available. When the data is read by the external system, this bit
will be cleared by the SL11R hardware. When a new word is available, the OF bit will again be set.\
Document #: 38-08006 Rev. **
1. INBUFF Data Register
2. OUTBUFF Data Register
3. STATUS Register
(0xC0C4; SL11R Read)
(0xC0C4; SL11R Write)
(0xC0C2: Read Only)
ADDR/GPIO19
ADDR/GPIO19
nWR/GPIO17
nCS/GPIO18
nCS/GPIO18
nRD/GPIO16
Mailbox and DMA Overview
Mailbox Interface
SD15-0
Internal Data Bus
CLR_INBUFF_FULL
Figure 3-2. Functional Logic Diagram
Reset
(1 of 16)
(1 of 16)
D
D
Q
Q
Fig.2 - Output Data Enable
Fig.1 - Input Data Latch
Internal Data Bus
INBUFF_FULL
(Reg 0xC0C2 Bit1)
SD15-0
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SL11R