SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 41

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

5.2.1
The physical interface for the Mailbox is shared with the DMA data path on the SD15-SD0 bus. When accessing the Mailbox
INBUFF & OUTBUFF registers, the ADDR pin should be driven high. The ADDR pin should be driven low to access the Mailbox
STATUS register. The external processor and SL11R can both access the INBUFF, OUTBUFF & STATUS Mailbox registers. The
SL11R includes two interrupt vectors for this Mailbox Protocol. Whenever the external Processor accesses the Mailbox, the
associated interrupt will be generated.
Note:
5.2.2
The external processor will write to this register with the ADDR signal set to one and the SL11R will read this register after
receiving the interrupt (if the MBX interrupt is enabled in the Register 0xC00E).
5.2.3
The SL11R will write to this register and the external processor will read from this register with the ADDR signal set to one. The
SL11R will receive an interrupt after the external processor finished reading (if the MBX interrupt is enabled in the Register
0xC00E).
Document #: 38-08006 Rev. **
• To enable the Mailbox interrupt, the bit MBX in the Register 0xC00E must be enabled.
• The external processor cannot access the Mailbox while DMA is in progress.
D15-0
D15-0
Mailbox Protocol
INBUFF Data Register (0xC0C4: R/W)
OUTBUFF Data Register (0xC0C4: R/W)
D15
D15
D15
D15
D14
D14
D14
D14
D15-0
D15-0
SD15-0
D13
D13
D13
D13
D12
D12
D12
D12
Figure 5-2. 8/16-bit DMA Mode Block Diagram
Data from input Mailbox
Data for Output Mailbox
OUTBUFF
STATUS
INBUFF
D11
D11
D11
D11
D10
D10
D10
D10
D9
D9
D9
D9
D8
D8
D8
D8
D7
D7
D7
D7
DATA15-0
D6
D6
D6
D6
D5
D5
D5
D5
PROCESSOR
D4
D4
D4
D4
SL11R
D3
D3
D3
D3
D2
D2
D2
D2
D1
D1
D1
D1
D0
D0
D0
D0
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SL11R