SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 59

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

7.9
This section describes in detail the six-operand field bits referred to in the previous section as source and destination. Bear in
mind that although the discussion refers to bits 0 through 5, the same bit definitions apply to the “source” operand field, bits 6
through 11. These are the basic addressing modes in the SL11R Processor.
Notes:
7.10
In register addressing, any one of registers R0-R15 can be selected using bits 0-3. If register addressing is used, operands are
always 16-bit operands, since all registers are 16-bit registers. For example, an instruction using register R7 as an operand would
fill the operand field like this:
7.11
In Immediate Addressing, the instruction word is immediately followed by the source operand. For example, The operand field
would be filled with:
Note:
In immediate addressing, the source operand must be 16 bits wide, eliminating the need for a b/w bit.
7.12
In Direct Addressing, the word following the instruction word is used as an address into RAM. Again, the operand can be either
byte or word sized, depending on the state of bit 3 of the operand field. For example, to do a word-wide read from a direct address,
the source operand field would be formed like this:
Note:
For a memory-to-memory move, the instruction word would be followed by two words, the first being the source address and the
second being the destination.
7.13
Indirect addressing is accomplished using address registers R8-15. In Indirect addressing, the operand is found at the memory
address pointed to by the register. Since only eight address registers exist, only three bits are required to select an address
register. For example, register R10 (binary 1010) can be selected by ignoring bit 3, leaving the bits 010. Bit 3 of the operand field
Document #: 38-08006 Rev. **
Register
Immediate
Direct
Indirect
Indirect with Auto Increment
Indirect with Index
Register Operand
Operand field
I/O operand
• b/w: ‘1’ for byte-wide access, ‘0’ for word access.
• Indirect with auto increment and byte-wide Indirect addressing is illegal with the stack pointer (R15).
Addressing Modes
Register Addressing
Immediate Addressing
Direct Addressing
Indirect Addressing
Bits
Bits
Bits
Mode
5
0
5
0
5
1
5 4
0 0
0 1
1 0 b/w 1 1 1
0 1 b/w
1 0 b/w
1 1 b/w
4
0
4
1
4
0
3
1
r
3
0
3
1
3
0
2 1 0
1 1 1
r
r
r
r
2
1
2
1
2
1
r
r
r
r
r
r
r
r
1
1
1
1
1
1
0
1
0
1
0
1
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SL11R