SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 31

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

4.14.4
This register contains the Page 2 high order address bits. These bits are always appended to accesses to the Page 2 Memory
mapped space. The default is 0x0000.
4.14.5
A multiplexed address port and 16-bit data port are provided to interface to an external 256Kx16 or a 1Megx16 EDO DRAM. The
port provides nRAS, nCASL, nCASH, nDRAMWR and nDRAMOE control signals for data access and refresh cycles to the DRAM.
This register is designed to control the DRAM interface.
Note:
4.14.6
The total memory space allocated by the SL11R is 64K-bytes. Program, data, and I/O space are contained within a 64K-byte
address space. The program code or data can be stored in either external RAM or external ROM.
The SL11R allows extended data (video) to be stored on an external EDO DRAM. The entire (video image) data can be transferred
via DMA directly to DRAM without software intervention. The total DMA size can be up-to 2M-bytes. The SL11R processor can
access DRAM data via the address space from 0x8000 to 0xBFFF.
The SL11R Controller provides a 16-bit Memory interface that can support a wide variety of external DRAM, RAM and ROM
devices. The SL11R Controller memory space is byte addressable and is divided as follows:
Document #: 38-08006 Rev. **
• Most of EDO and Page mode DRAM can be used as long as the CAS signal is issued before the RAS signal.
• Page mode access allows multiple CAS addresses to be issued within 1 Row address. The Page really corresponds to the
Row. Once the Row address has been accessed, any accesses to that Page can be made without issuing the Row address
again. Only the Column address is necessary. This allows for faster read and write accesses to the same page.
If Bit A21 is ‘1’,
If bit A21 is ‘0’
D8-0
If Bit A21 is ‘1’,
If bit A21 is ‘0’
D8-0
D2
D1
D0
D15
Extended Page 2 Map Register (0xC01A: R/W)
DRAM Control Register (0xC038: R/W)
Memory Map
0
D14
0
A21-13
D13
A21-13
DT
PE
RE
0
D12
0
D11
D15-D7
0
Page 1 reads/writes will access external DRAM
Page 1 reads/writes will access some other external area (SRAM, ROM or peripherals).
nXMEMSEL will be the external Chip Select for this space.
Page 1 high order address bits. The address pins on A21-A13 will reflect the content of
this register when SL11R accesses the address 0x8000-0x9FFF.
Page 2 reads/writes will access external DRAM
Page 2 reads/writes will access some other external area (SRAM, ROM or peripherals)
and nXMEMSEL will be the external Chip Select for this space.
Page 2 high order address bits. The address pins on A21-A13 will reflect the content of
this register when SL11R access the address 0xA000-0xBFFF.
DRAM Turbo, Enable when set = '1'. Uses 1 clock for CAS instead of 2.
DRAM Page Mode Enable when set = '1'.
DRAM Refresh Enable when set = '1'.
0
D10
0
D6
0
D9
0
D5
0
A21
D8
D4
0
A20
D7
D3
0
A19
D6
DT
D2
A18
D5
PE
D1
A17
D4
RE
D0
A16
D3
A15
D2
A14
D1
Page 31 of 85
A13
D0
SL11R