SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 21

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

4.9.11
See USB Endpoint 0 Count Register (0x0122: R/W)
4.10
The SL11R provides software control registers that can be used to configure the chip mode, clock control, read software version
and software breakpoint control.
4.10.1
The Configuration Register is used to configure the SL11R into the appropriate mode, and to select a clock multiplier.
Note: D6-4 and C2-0 are Clock Configuration bits. These bits select the clock source. The clock may come from an outside pin
(X1 or X_PCLK) or it may come from the PLL multiplier as indicated in the table.
Note:
Note:
By default, this bit will be set to zero by the SL11R BIOS.
Document #: 38-08006 Rev. **
• On the SL11R chip set, this bit will be set to zero.
• `There are four modes defined in this documentation: DVC 8-bit DMA mode, Fast EPP mode, 8/16-bit DMA mode and General
C2
0
0
0
0
1
1
1
1
Purpose IO (GPIO) mode. All modes are pin-compatible.
M1
0
0
1
1
D3
If Clock Disable bit = ‘1’, this Clock Configuration register can no longer be modified through software writes. It is a “sticky
bit” used to lock the configuration through a write to this bit in the boot prom code.
D2, D1
D0
If Mode Disable bit = ‘1’, this Configuration register can no longer be modified through software writes. It is a “sticky bit”
used to lock the configuration through a Write to this bit in the boot prom code.
D15-D7
D15
0
USB Endpoint 3 Count Register (0x012E: R/W)
Processor Control Registers
Configuration Register (0xC006: R/W)
C1
0
0
1
1
0
0
1
1
M0
D14
0
1
0
1
0
C0
0
1
0
1
0
1
0
1
D13
CD
MD
Reserved
0
M1,M0:
X_PCLK
2/3*X1
2/3*X1
8/3*X1
8/3*X1
PCLK
4*X1
4*X1
X1
D12
DVC 8-Bit DMA
0
8/16-Bit DMA
Fast EPP
Mode
GPIO
D11
RCLK
4*X1
4*X1
4*X1
4*X1
0
X1
X1
X1
X1
SL11R modes are selected as shown here:
should be set to all zeros.
D10
0
OE
0
0
0
1
0
0
1
1
D9
0
D8
0
D7
0
D6
C2
D5
C1
D4
C0
CD
D3
M1
D2
D1
M0
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SL11R
MD
D0