SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 13

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

3.18
This interface uses the same hardware as the Mailbox Interface, except that the DMA engine inside the SL11R generates DMA
requests to control the transfer. Because the DMA engine handles the transfer of data through the Input and Output buffer, there
is no need for the external system to poll the status register. The external system simply waits for a DREQ (GPIO 20) from the
SL11R and transfers data. The SL11R DMA engine can transfer data in only one direction at a time. Please note that only 16-bit
DMA transfers are supported on the SL11R.
The 22-bit DMA counter is loaded through registers 0xC02C and 0xC02E. This makes up the DMA start address and the location
of the first word to be written or read. The 22-bit DMA end address register is loaded through registers 0xC030 and 0xC032. This
will be location of the last word written into the SL11R. When reading data out of the SL11R, the end address register should be
loaded with the last address to be read from plus two. After these registers are loaded, the DMA control register (0xC0C0) must
be loaded with a 0x0007 to enable the DREQ output pin. Lastly, the other DMA control register (0xC02A) is loaded with either a
0x0001, to start DMA transfers into the SL11R, or 0x0003, to start DMA transfers out of the SL11R.
Document #: 38-08006 Rev. **
t
t
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t
t
t
CDQ
APW
CPW
RPW
RAH
RCH
ACC
DCS
DR
RHDQ
RDH
Parameter
DMA Interface
PCLK to DREQ high
ADDR pulse width
nCS pulse width
Read pulse width
ADDR hold after read high
nCS hold after read high
Read access time
DREQ high to CS low
DREQ high to read low
Read high to DREQ low hold
Read high to data hold
DREQ/GPIO20
ADDR/GPIO19
nRD/GPIO16
nCS/GPIO18
SD15-0
PCLK
Description
t
CDQ
Figure 3-3. Mailbox/DMA Read
t
t
DCS
DR
t
ACC
t
RPW
DATA VALID
Min.
t
t
APW
CPW
30
30
30
1
0
0
5
5
t
t
RAH
RCH
Typical
t
RDH
t
RHDQ
Max.
17
25
30
10
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SL11R
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns