SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 32

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

Table 4-5. Memory Map
Notes:
Document #: 38-08006 Rev. **
8.
9.
Memory Mapped Registers
Extended Page 1/DRAM
Extended Page 2/DRAM
The External RAM address from 0x0000 to 0x0C00 will not be accessible from the SL11R processor. This is an overlay memory space between internal RAM
and external RAM. The addressable external RAM will occupy from 0x0C00-0x7FFF, which is 29K-byte. The signal name nXRAMSEL on SL11R-pin56 will be
active when the CPU access address from 0x0C00 to 0x7FFF.
When bit 12 (ROM Merge Bit) of the Extended Memory Controller Register at address 0xC03A is ‘0’, then the External ROM address space will be mapped from
0xC100 to 0xE7FF. The address from 0x8000 to 0xC100 and the address from 0xE800 to 0xFFFF are the overlay memory spaces. The actual total size of the
external ROM will be (0xE800-0xC100), which is 9.75K-byte. The signal nXROMSEL on the SL11R (pin57) will be active when the CPU accesses the address
from 0xC100 to 0xE7FF. The signal nXMEMSEL on the SL11R (pin58) will be active when the CPU accesses the address from 0x8000 to 0xBFFF. When bit 12
(ROM Merge Bit) of the Extended Memory Controller Register at address 0xC03A is ‘1’, then the External ROM address space will be mapped into these windows:
0x8000 to 0xBFFF and 0xC100 to 0xE7FF. The address from 0xC000 to 0xC100 and the address from 0xE800 to 0xFFFF are the overlay memory spaces. The
actual total size of the external ROM will be (0xC000-0x8000) and (0xE800-0xC100), which is 16K-byte + 9.75K-bytes, or 25.75K.
Bit 12 (ROM Merge) of the Extended Memory
External ROM
Each External memory space can be 8 or 16 bits wide, and can be programmed to have up to 7
wait-states.
External RAM
Internal ROM
Internal RAM
Function
Controller Register = 0
0xC100 to 0xE7FF
0xC000 to 0xC0FF
0xA000 to 0xBFFF
Actual External
0x8000 to 0x9FFF
Unused Overlay
Unused Overlay
Unused Overlay
ROM (16Kx16)
Memory Space
Memory Space
Memory Space
ROM
or
0xC100 – 0xE7FF
0x0C00 – 0x7FFF
0xA000 – 0xBFFF
0xC000 – 0xC0FF
0x0000 – 0x0BFF
0xE800 – 0xFFFF
0x8000 – 0x9FFF
Address
0x0C00 to 0x7FFF
[8]
[9]
0x0000 to 0x0C00
Actual External
SRAM (16Kx16)
Unused Overlay
Memory Space
RAM
or
Bit 12 (ROM Merge) of the Extended Memory
Controller Register = 1
0xC100 to 0xE7FF
0x8000 to 0xBFFF
0xC000 to 0xC0FF
Actual External
Unused Overlay
Memory Space
ROM (16Kx16)
External
Actual
ROM
ROM
or
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SL11R