SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 18

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

4.5
The SL11R has a built-in transceiver that meets the USB specification v1.1. The transceiver connects directly to the physical layer
of the USB engine. It is capable of transmitting or receiving serial data at the USB maximum data rate of 12 Mbits/sec. The SL11R
has four USB DMA engines for four USB endpoints. Each of the USB DMA engines is independently responsible for its respective
USB transaction. The 16-bit processor has the ability to set up pointers and block sizes in buffer memory for USB transactions.
The SL11R Controller contains a number of Registers that provide overall control and status functions for USB transactions. The
first set of registers is for control and status functions, while the second group is dedicated to specific endpoint functions. Com-
munication and data flow on the USB is implemented using endpoints. These uniquely identifiable entities are the terminals of
communication flow between a USB host and USB devices. Each USB device is composed of a collection of independently
operating endpoints. Each endpoint has a unique identifier: the endpoint number. (See USB specification v1.1. Sec 5.3.1)
The SL11R also includes the SL11R BIOS that provides a set of subroutines via interrupt calls for all USB interface functions
required to communicate with a USB host (refer to [Ref. 1] SL11R_BIOS for more information). The SL11R BIOS greatly simplifies
the firmware/software development cycle.
4.5.1
The USB Global Control & Status Register allows high-level control and provides status of the USB-DMA engines. The Global
Control & Status register bits are defined as follows:
Notes:
4.5.2
The Frame Number Register contains the 11-bit ID Number of the last SOF received by the device from the USB Host.
Note:
4.5.3
Address Register holds the USB address of the device assigned by the Host - initialized to address 0x0000 upon Power up.
Document #: 38-08006 Rev. **
• Suspend state should be entered if there is no activity after 3mS (UA).
• The US and UA bits are automatically cleared after they are read by the SL11R processor.
• D15-D4 are the reserved bits, should be written with zeros.
• The SL11R BIOS will set the UE=1 upon reset.
• The SL11R BIOS uses this register to detect USB activity for the internal idle task.
D15-D4
D0
D1
D2
D3
D15-D11
D10-D0
D15
D15
D15
0
0
0
USB Interface
USB Global Control & Status Register (0xC080: R/W)
USB Frame Number Register (0xC082: Read Only)
USB Address Register (0xC084: R/W)
D14
D14
D14
0
0
0
D13
D13
D13
Reserved
UE
UR
US
UA
Reserved
S10-S0
0
0
0
D12
D12
D12
0
0
0
D11
D11
D11
0
0
0
USB Enable = ’1’, Overall USB enable/disable bit
USB Reset
USB SOF
USB Activity = ’1’, Activity Seen
set to all zeros.
SOF ID Number of last SOF Received
D10
D10
S10
D10
0
0
D9
D9
S9
D9
0
0
= ’1’, USB received SOF command
= ’1’, USB received Reset command
D8
D8
S8
D8
0
0
D7
D7
D7
S7
0
0
D6
D6
S6
D6
A6
0
D5
D5
S5
D5
A5
0
D4
D4
D4
S4
A4
0
UA
D3
D3
S3
D3
A3
US
D2
D2
S2
D2
A2
UR
D1
D1
D1
S1
A1
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SL11R
UE
D0
D0
S0
D0
A0