SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 66

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

7.22
Notes:
Document #: 38-08006 Rev. **
10. The number in the “clock cycles” column reflects the number of clock cycles for register or immediate accesses. For each occurrence of other types of accesses,
11. All clock cycle values assume zero wait-states.
12. A shift of one is done in four clock cycles, each additional shift adds two more clock cycles.
MOV
ADD
ADDC
SUB
SUBB
CMP
AND
TEST
OR
XOR
Jcc
JccL
Rcc
Ccc
Int
SHR
SHL
ROR
ROL
ADDI
SUBI
NOT
NEG
CBW
STI
CLI
STC
CLC
Mnemonic
include the appropriate “clock adder” as listed in the Addressing Modes table below.
SL11R Processor Instruction Set Summary
s,d
s,d
s,d
s,d
s,d
s,d
s,d
s,d
s,d
s,d
c,v
c,d
c
c,d
v
n,d
n,d
n,d
n,d
n,d
n,d
d
d
d
Operands
Move s to d
Add s to d
Add s to d with carry
Subtract s from d
Subtract s from d with carry
Compare d with s
AND d with s
Bit test d with s
OR d with s
XOR d with s
Jump relative on condition ’c’
Jump absolute on condition ’c’
Return on condition ’c’
Call subroutine on condition ’c’
Software interrupt
Shift right out of carry
Shift left into carry
Rotate right
Rotate left
Add immediate
Subtract immediate
1’s complement
2’s complement
Sign-extend d(7:0) to d(15:0)
Enable interrupts
Disable interrupts
Set carry
Clear carry
Description
0000 ssss ssdd dddd
0001 ssss ssdd dddd
0010 ssss ssdd dddd
0011 ssss ssdd dddd
0100 ssss ssdd dddd
0101 ssss ssdd dddd
0110 ssss ssdd dddd
0111 ssss ssdd dddd
1000 ssss ssdd dddd
1001 ssss ssdd dddd
1100 cccc 0ooo oooo
1100 cccc 10dd dddd
1100 cccc 1001 0111
1010 cccc 10dd dddd
1010 0000 0vvv vvvv
1101 000n nndd dddd
1101 001n nndd dddd
1101 010n nndd dddd
1101 011n nndd dddd
1101 100n nndd dddd
1101 101n nndd dddd
1101 1110 00dd dddd
1101 1110 01dd dddd
1101 1110 10dd dddd
1101 1111 1100 0000
1101 1111 1100 0001
1101 1111 1100 0010
1101 1111 1100 0011
MSb
Opcode
LSb
Affected
Z,C,O,S
Z,C,O,S
Z,C,O,S
Z,C,O,S
Z,C,O,S
Z,O,C,S
Flags
Z,C,S
Z,C,S
Z,C,S
Z,C,S
None
None
None
None
None
None
None
None
Z,S
Z,S
Z,S
Z,S
Z,S
Z,S
Z,S
Z,S
C
C
Cycles
Clock
5
5
5
5
5
5
5
5
5
5
3
4
7
7
7
4
4
4
4
4
4
4
4
4
3
3
3
3
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SL11R
10,12,11
10,12,11
10,12,11
10,12,11
Notes
10,11
10,11
10,11
10,11
10,11
10,11
10,11
10,11
10,11
10,11
11
11
11
11
11
11
11
11
11
11
11
11
11
11