SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 30

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SL11R

Manufacturer Part Number
SL11R
Description
IC MCU FULL SPD USB 16B 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of SL11R

Applications
USB Microcontroller
Core Processor
RISC
Program Memory Type
Mask ROM (6 kB)
Controller Series
USB Controller
Ram Size
3Kx8
Interface
2-Wire Serial, UART, USB
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 65°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1462

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Note:
The external memory devices can be 8 or 16 bits wide, and can be programmed to have up to 7 wait-states. External SRAM/PROM
requires one wait state.
4.14.1
This register provides control of Wait States for the internal RAM and ROM.
4.14.2
This register provides control of Wait States for the external SRAM/DRAM/EPROM.
Note:
The default Wait State setting on power up or reset is 7 wait states.
4.14.3
This register contains the Page 1 high order address bits. These bits are always appended to accesses to the Page 1 Memory
mapped space. The default is 0x0000.
Document #: 38-08006 Rev. **
xrom_ok:
xram_ok:
D15
D2
D1
D0
0
D12
D11
D10-8
D7
D6-4
D3
D2-0
D15
0
mov
cmp
je
or
Memory Control Register (0xC03E: R/W)
Extended Memory Control Register (0xC03A: R/W)
Extended Page 1 Map Register (0xC018: R/W)
D14
D15
0
0
D14
0
[0xC00],0xC3B6
[0xC00],0xC3B6
xram_ok
[0xC03A],8
D13
D14
0
0
D13
RA
RO
DB
RM
EM3
EM2-0
RO3
RO2-0
RA3
RA2-0
0
D12
RM
D13
0
D12
0
EM3
D11
D12
0
D11
0
;check 0xC3B6 for 16-bit RAM
;set for 8-bit external RAM
If ‘1’, one-wait state for internal RAM is added
If ‘1’, one-wait state for internal ROM is added
If ‘1’, DEBUG mode is enabled. Internal address bus is echoed to external address pins.
ROM Merge. If ‘1’, nXROMSEL is active if nXMEMSEL is active.
Extended Memory Width ('0' = 16, '1' = 8)
Extended Memory Wait states (0 - 7)
External ROM Width ('0' = 16, '1' = 8)
External ROM wait states (0 - 7)
External RAM Width ('0' = 16, '1' = 8)
External RAM Wait States (0 - 7)
EM2
D11
D10
0
D10
0
D10
EM1
D9
0
D9
0
D9
EM0
0
A21
D8
D8
D8
0
A20
RO3
D7
D7
D7
0
A19
RO2
D6
D6
D6
0
A18
D5
RO1
D5
D5
0
D4
A17
D4
0
RO0
D4
D3
0
A16
D3
RA3
D3
RA
D2
A15
D2
RA2
D2
RO
D1
A14
D1
RA1
D1
DB
D0
Page 30 of 85
A13
SL11R
D0
RA0
D0

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