SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 20

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

4.9.3
Reading the Endpoint Status Register provides Status information relative to the packet that has been received or transmitted.
The register is defined as follows:
Notes:
4.9.4
This is the pointer to memory buffer location for USB reads and writes to this Endpoint. At the end of any transfer, this register
will contain its original value plus the value in the USB Endpoint Count Register.
4.9.5
See USB Endpoint 0 Address Register (0x0120: R/W)
4.9.6
See USB Endpoint 0 Address Register (0x0120: R/W)
4.9.7
See USB Endpoint 0 Address Register (0x0120: R/W)
4.9.8
This register is used to set the maximum packet size for the USB transfer. At the end of a successful transfer, the USB endpoint
Count Register is set to zero.
4.9.9
See USB Endpoint 0 Count Register (0x0122: R/W)
4.9.10
See USB Endpoint 0 Count Register (0x0122: R/W)
Document #: 38-08006 Rev. **
• Endpoint 0 is set up as a control endpoint. The DIR bit is read-only, and indicates the direction of the last completed transaction.
• At the end of any transfer to an armed and enabled endpoint (with the correct DIR bit), an interrupt occurs, and vectors to a
• The DATA0/DATA1 bit is automatically toggled by the hardware. To reset this DATA0/DATA1 toggle bit to DATA0, the Enable on
• When the Zero Length bit (D5) is set, the host will receive the zero length USB packet, regardless of the number of bytes in
• The SL11R BIOS has full control of USB endpoint 0. The SL11R BIOS responds to all numeration from the host. On other
• The SL11R BIOS will set all USB Control & Status registers for endpoint 1 through 3 to zero upon receiving the SET_CONFIG
Bit Position
If the direction is incorrect, it is the firmware’s responsibility to handle the error. On other endpoints, DIR bit is written, and if
the direction of the transfer does not match the DIR bit, then the transaction is ignored.
different location depending upon whether an error occurred or not. At the end of this transfer, the corresponding endpoint is
disarmed (the Arm bit is cleared), and the DATA0/DATA1 toggle bit is advanced if no error occurred. If a packet is received with
an incorrect toggle state, the packet is ignored so that the host will re-send the data.
the D1 bit should be cleared to ‘0’ and then set to ‘1’.
the USB Count register.
endpoints, the SL11R BIOS can be used to control under BIOS interrupt calls (see [Ref. 1] SL11R_BIOS).
command from host. (See [Ref. 3] Universal Serial Bus Specification 1.11, Chapter 9 for more information.)
D5-D12
D13
D14
D15
D0
D1
D2
D3
D4
USB Endpoints Status (For Reading)
USB Endpoint 0 Address Register (0x0120: R/W)
USB Endpoint 1 Address Register (0x0124: R/W)
USB Endpoint 2 Address Register (0x0128: R/W)
USB Endpoint 3 Address Register (0x012C: R/W)
USB Endpoint 0 Count Register (0x0122: R/W)
USB Endpoint 1 Count Register (0x0126: R/W)
USB Endpoint 2 Count Register (0x012A: R/W)
Bit Name
Not used
Enable
Setup
Done
Error
Stall
Arm
DIR
ISO
If '1', the endpoint is armed
If '1', the endpoint is enabled
Direction bit. If '1', set to transmit to Host (IN). If '0', set to receive from Host (OUT)
If ‘1’, isochronous mode selected for this endpoint
If '1', endpoint will send stall on USB when requested
Read returns logic ‘0’s
If '1', a Setup packet has been received
If '1', an error condition occurred on last transaction for this endpoint
If '1', transaction completed. Arm Bit is cleared to '0' when Done Set
Function
Page 20 of 85
SL11R